In recent years, there is a high demand for a high speed and low power consumption of a semiconductor device, particularly for a dynamic random access memory (DRAM). In order to meet this demand, a polymetal gate structure and a dual-gate structure are employed.
The polymetal gate structure has metal films laminated on a polycrystalline silicon film. The polymetal gate structure can have lower resistance than that of a polycide gate structure that has been conventionally used. In general, the polymetal gate structure has a barrier metal (such as a tungsten nitride (WN) film), and a metal film (such as a tungsten (W) film), laminated together on the polycrystalline silicon film. However, this polymetal gate structure has a problem in that interface resistance, that is, contact resistance between the barrier metal film and the polycrystalline silicon film, becomes nonlinearly high. Therefore, the polymetal gate structure having the silicide film present between the polycrystalline silicon film and the barrier metal film has come to be employed.
On the other hand, according to the dual-gate structure, a gate electrode that contains N-type polycrystalline silicon having N-type impurities (such as phosphorus) implanted in the polycrystalline silicon, is used for the gate electrode of an NMOS transistor, and a gate electrode that contains P-type polycrystalline silicon having P-type impurities (such as boron) implanted in the polycrystalline silicon, is used for the gate electrode of a PMOS transistor. Because the PMOS transistor has a surface-channel type in the dual-gate structure, a short-channel effect can be suppressed when the gate length is short. This is advantageous in increasing the performance of the transistor. Furthermore, because a threshold level can be decreased from that of the conventional embedded channel-type MOS transistor, the driving voltage can be lowered.
A conventional method of manufacturing the gate electrodes having the polymetal gate structure and the dual-gate structure will be explained with reference to FIGS. 12 to 20. In FIGS. 12 to 20, a “region N” represents a region where the gate electrode containing N-type polycrystalline silicon is formed, and a “region P” represents a region where the gate electrode containing P-type polycrystalline silicon is formed.
First, as shown in FIG. 12, a silicon oxide film 202a is formed on the surface of a silicon substrate 201 by thermal oxidation. Next, as shown in FIG. 13, the silicon oxide film 202a is nitrided by plasma nitrization, thereby forming a gate oxynitride film 202.
Next, as shown in FIG. 14, an amorphous silicon film 203a is formed on the gate oxynitride film 202.
Next, as shown in FIG. 15, the region P is covered with a resist film 204, and phosphorus is ion-implanted as N-type impurities into the region N. Thereafter, the resist film 204 is removed.
Next, as shown in FIG. 16, the region N is then covered with a resist film 205, and boron is ion-implanted as P-type impurities into the region P.
As shown in FIG. 17, after the resist film 205 is removed, a tungsten silicide (WSi) film 206 is formed on the whole surface of the amorphous silicon film 203a, according to a CVD method using a mixed gas of WF6 and SiH2Cl2. The WSi film 206 can be also formed by a physical vapor deposition (PVD) method such as sputtering. However, when the PVD method is used, oxygen is mixed into the film, and the oxygen increases sheet resistance of the WSi film. The CVD method is therefore used.
As shown in FIG. 18, a rapid thermal annealing (RTA) is carried out in the atmosphere of 700 to 950° C. for 10 to 60 seconds, as what is called degasification, to discharge gases of chlorine, fluorine and so on that remain in the WSi film 206 formed in the CVD method, to the outside. By this RTA, the N-type impurities and the P-type impurities that are implanted into the amorphous silicon 203a are simultaneously activated, and the amorphous silicon film 203a is converted into a polycrystalline silicon film. Consequently, an N-type polycrystalline silicon film 203n and a P-type polycrystalline silicon film 203p are formed on the gate oxynitride film 202, respectively.
Next, as shown in FIG. 19, a tungsten nitride (WN) film 207 and a tungsten (W) film 208 are sequentially formed on the WSi film 206 by sputtering. Furthermore, a silicon nitride film 209 of a gate electrode pattern is formed on the tungsten (W) film 208. Thereafter, as shown in FIG. 20, the W film 208, the WN film 207, tungsten silicide (WSi) film 206 and the polycrystalline silicon films 203n and 203p are patterned, using the silicon nitride film 209 as a mask, thereby completing an N-type polymetal gate electrode 210n and a P-type polymetal gate electrode 210p. 
Methods of manufacturing the semiconductor device having the gate electrodes of the polymetal gate structure and the dual-gate structure are described in, for example, Japanese Patent Application Laid-open Nos. 2000-77540, H8-306802, H9-51040, H9-190983, and H9-246206.
FIG. 21 is a graph showing a relationship between the RTA temperature when degassing the WSi film 206, the interface resistance of the N-type polymetal gate electrode 210n (the contact resistance between the N-type polycrystalline silicon 203n and the WSi film 206), and the interface resistance of the P-type polymetal gate electrode 210p (the contact resistance between the P-type polycrystalline silicon 203p and the WSi film 206). “N-gate” represents the interface resistance of the N-type polymetal gate electrode 210n, and “P-gate” represents the interface resistance of the P-type polymetal gate electrode 210p. A value 1.0 in the vertical axis represents a standard value of the interface resistance.
As shown in FIG. 21, according to the above conventional manufacturing method, there is no temperature range of RTA in which both the interface resistance of the N-type polymetal gate electrode 210n and the interface resistance of the P-type polymetal gate electrode 210p satisfy the standard value of the interface resistance. In the temperature range where the interface resistance of the N-type polymetal gate electrode 210n satisfies the standard value, the interface resistance of the P-type polymetal gate electrode 210p becomes very high as compared with the interface resistance of the N-type polymetal gate electrode 210n. 
As explained above, when there is a large difference between the interface resistance of the N-type polymetal gate electrode and the interface resistance of the P-type polymetal gate electrode, the following problems arise.
FIGS. 22A and 22B show a ring oscillator circuit. FIG. 22A shows a circuit symbol, and FIG. 22B shows a circuit diagram. As shown in FIG. 22A, an output OUT of an inverter 300 returns to an input IN. As shown in FIG. 22B, the inverter 300 includes a PMOS transistor 301 and an NMOS transistor 302. These gate electrodes employ a polymetal gate structure and a dual-gate structure.
In the ring oscillator circuit as shown in FIGS. 22A and 22B, when the interface resistance of the polymetal gate electrode of the PMOS transistor 301 is much higher than the interface resistance of the polymetal gate electrode of the NMOS transistor 302 (corresponding to a region A shown in FIG. 21), as shown in FIG. 23A, the waveform of the rise of the output signal OUT is slowed down to a large extent as compared with the waveform of the input signal IN. On the other hand, when the interface resistance of the polymetal gate electrode of the NMOS transistor 302 is much higher than the interface resistance of the polymetal gate electrode of the PMOS transistor 301 (corresponding to a region B shown in FIG. 21), as shown in FIG. 23B, the waveform of the fall of the output signal OUT is slowed down to a large extent as compared with the waveform of the input signal IN.